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| CY26114 One-PLL Clock Generator Features * Integrated phase-locked loop * Low skew, low jitter, high accuracy outputs * 3.3V Operation with 2.5 V Output Option Part Number CY26114 Outputs 4 Input Frequency 25MHz Crystal Input Benefits Internal PLL with up to 333 MHz internal operation Meets critical timing requirements in complex system designs Enables application compatibility Output Frequency Range 2 copies of 100MHz, 1 copy of 50MHz, 1 copy 25/33/50/66MHz (frequency selectable) Logic Block Diagram XIN XOUT P OSC. Q VCO OUTPUT MULTIPLEXER AND DIVIDERS 100MHz 100MHz 50MHz Pin Configurations 16-pin TSSOP XIN VDD AVDD FS0 AVSS VSSL LCLK1 LCLK2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XOUT CLK4 CLK3 VSS N/C VDDL FS1 N/C PLL FS0 FS1 25/33/50/66MHz (frequency selectable) VDDL VDD AVDD AVSS VSS VSSL CLK4 Frequency Select Options FS1 0 0 1 1 FS0 0 1 0 1 CLK 4 25 33 50 66 Units MHz MHz MHz MHz Cypress Semiconductor Corporation Document #: 38-07098 Rev. *A * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised December 14, 2002 CY26114 Pin Definitions Name XIN VDD AVDD FS0 AVSS VSSL LCLK1 LCLK2 N/C FS1 VDDL N/C VSS CLK3 CLK4 XOUT Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description Reference Crystal Input Voltage Supply Analog Voltage Supply Frequency Select 0 Analog Ground LCLK Ground 100-MHz output clock at VDDL Level 100-MHz output clock at VDDL Level No Connect Frequency Select 1 LCLK Voltage Supply (2.5V or 3.3V) No Connect Ground 50-MHz output clock 25/33/50/66-MHz clock output (frequency selectable) Reference Crystal Output Absolute Maximum Conditions Parameter VDD VDDL TJ Description Supply Voltage I/O Supply Voltage Junction Temperature Digital Inputs Digital Outputs referred to VDD Digital Outputs referred to VDDL Electro-Static Discharge AVSS - 0.3 VSS - 0.3 VSS - 0.3 2 Min. -0.5 Max. 7.0 7.0 125 AVDD + 0.3 VDD + 0.3 VDDL +0.3 Unit V V C V V V kV Recommended Operating Conditions Parameter VDD VDDL TA CLOAD fREF tPU Description Operating Voltage Operating Voltage Ambient Temperature Max. Load Capacitance Reference Frequency Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 0.05 25 500 Min. 3.0 2.375 0 Typ. 3.3 2.5 Max. 3.6 2.625 70 15 Unit V V C pF MHz ms Note: 1. Float XOUT if XIN is externally driven. Document #: 38-07098 Rev. *A Page 2 of 5 CY26114 DC Electrical Characteristics Parameter[2] IOH IOL IOH IOL VIH VIL IVDD IVDDL IVDDL Name Output High Current Output Low Current Output High Current Output Low Current Input High Voltage Input Low Voltage Supply Current Supply Current Supply Current Description VOH = VDD - 0.5, VDD/VDDL = 3.3V VOL = 0.5, VDD/VDDL = 3.3V VOH = VDDL - 0.5, VDDL=2.5V VOL = 0.5, VDDL = 2.5V CMOS levels, 70% of VDD CMOS levels, 30% of VDD AVDD/VDD Current VDDL Current (VDDL = 3.6V) VDDL Current (VDDL = 2.625V) Min. 12 12 8 8 0.7 0.3 25 20 15 Typ. 24 24 16 16 Max. Unit mA mA mA mA VDD VDD mA mA mA AC Electrical Characteristics Parameter[2] DC t3 t3 t4 t4 t5 t9 t10 Name Output Duty Cycle Rising Edge Rate Rising Edge Rate Falling Edge Rate Falling Edge Rate Skew Clock Jitter PLL Lock Time Description Duty Cycle is defined in Figure 1; t1/t2, 50% of VDD Output Clock Rise Time, 20% - 80% of VDD/VDDL = 3.3V Output Clock Rise Time, 20% - 80% of VDDL = 2.5V Output Clock Fall Time, 80% - 20% of VDD/VDDL = 3.3V Output Clock Fall Time, 80% - 20% of VDDL = 2.5V Delay between related outputs at rising edge Peak to Peak period jitter Min. 45 0.8 0.6 0.8 0.6 Typ. 50 1.4 1.2 1.4 1.2 250 200 3 Max. 55 Unit % V/ns V/ns V/ns V/ns ps ps ms t1 t2 CLK 50% 50% Figure 1. Duty Cycle Definitions: DC = t2/t1. t3 80% t4 CLK 20% Figure 2. Rise Time and Fall Time Definitions. Note: 2. Not 100% tested. Document #: 38-07098 Rev. *A Page 3 of 5 CY26114 Test Circuit VDD 0.1 F OUTPUTS CLK out CLOAD AVDD 0.1 F GND Ordering Information Ordering Code CY26114ZC Package Name Z16 Package Type 16-Pin TSSOP Operating Range Commercial Operating Voltage 3.3V Document #: 38-07098 Rev. *A Page 4 of 5 (c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY26114 Document Title: CY26114 One-PLL Clock Generator Document Number: 38-07098 REV. ** *A ECN NO. 107333 121867 Issue Date 08/28/01 12/14/02 Orig. of Change CKN RBI Description of Change New Data Sheet Power up requirements added to Operating Conditions Information Document #: 38-07098 Rev. *A Page 5 of 5 |
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